A unified reconfigurable floating-point arithmetic architecture based on CORDIC algorithm

被引：0

作者：

Li, Bingyi ^{[1
,2
]}

Fang, Linlin ^{[1
,2
]}

Xie, Yizhuang ^{[1
,2
]}

Chen, He ^{[1
,2
]}

Chen, Liang ^{[1
,2
]}

机构：

[1] Beijing Inst Technol, Sch Informat & Elect, Radar Res Lab, Beijing, Peoples R China

[2] Beijing Key Lab Embedded Real Time Informat Proc, Beijing, Peoples R China

来源：

2017 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY (ICFPT) | 2017年

关键词：

reconfigurable; floating-point; CORDIC; FPGA;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents the design methodology and implementation of reconfigurable coordinate rotation digital computer (CORDIC) architecture that can be configured to operate in different modes and rotations to achieve single-precision floating point division, multiplication and square-root operations. Through introducing pre- and post- processing, the float-point operations can be integrated into a unified CORDIC iteration procedure. According to the characteristics of different operations, we propose a pipeline-parallel mixed architecture to optimize the area-delay-efficiency. Finally, the prototype based on Xilinx XC7VX690T has been established to test the performance of the proposed design. The result shows the related error with arithmetic computation is less than 10(-6), and the resource-consumption of the proposed design is less than the sum of existing IP cores.

引用

页码：301 / 302

页数：2

共 50 条

[11] A Reconfigurable Hardware Architecture for Miscellaneous Floating-Point Transcendental Functions
Li, Peng
Jin, Hongyi
Xi, Wei
Xu, Changbao
Yao, Hao
Huang, Kai
ELECTRONICS, 2023, 12 (01)
[12] Design and Implementation of Quadruple Floating-Point CORDIC
Singh, Arun Kumar
Singh, Madhav Kumar
Ray, Kailash Chandra
2015 IEEE International Symposium on Nanoelectronic and Information Systems, 2015, : 286 - 290
[13] A Hardware Implementation of the PID Algorithm Using Floating-Point Arithmetic
Kulisz, Jozef
Jokiel, Filip
ELECTRONICS, 2024, 13 (08)
[14] Feasibility of floating-point arithmetic in FPGA based ANNs
Nichols, KR
Moussa, MA
Areibi, SM
COMPUTER APPLICATIONS IN INDUSTRY AND ENGINEERING, 2002, : 8 - 13
[15] Optimal Architecture of Floating-Point Arithmetic for Neural Network Training Processors
Junaid, Muhammad
Arslan, Saad
Lee, TaeGeon
Kim, HyungWon
SENSORS, 2022, 22 (03)
[16] Floating-point error analysis based on affine arithmetic
Fang, CF
Chen, TH
Rutenbar, RA
2003 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOL II, PROCEEDINGS: SPEECH II; INDUSTRY TECHNOLOGY TRACKS; DESIGN & IMPLEMENTATION OF SIGNAL PROCESSING SYSTEMS; NEURAL NETWORKS FOR SIGNAL PROCESSING, 2003, : 561 - 564
[17] Hardware Architecture for Particle Swarm Optimization using Floating-point Arithmetic
Munoz, Daniel M.
Llanos, Carlos H.
Coelho, Leandro dos S.
Ayala-Rincon, Mauricio
2009 9TH INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS DESIGN AND APPLICATIONS, 2009, : 243 - +
[18] QUANTIZATION ERRORS IN FLOATING-POINT ARITHMETIC
SRIPAD, AB
SNYDER, DL
IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND SIGNAL PROCESSING, 1978, 26 (05): : 456 - 463
[19] ARBITRARY PRECISION FLOATING-POINT ARITHMETIC
MOTTELER, FC
DR DOBBS JOURNAL, 1993, 18 (09): : 28 - &
[20] Fused Floating-Point Arithmetic for DSP
Swartzlander, Earl E., Jr.
Saleh, Hani H.
2008 42ND ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, VOLS 1-4, 2008, : 767 - +

← 1 2 3 4 5 →