An interface ASIC design using FPGA

被引：0

作者：

Luo, JJ

Deng, XC

机构：

来源：

1996 2ND INTERNATIONAL CONFERENCE ON ASIC, PROCEEDINGS | 1996年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An interface ASIC chip for smart stream tape recorder has been designed using CMOS gate array technology. It is realized by XILINX FPGA, and has good performance in a 1/4 inch stream tape recoder.

引用

页码：224 / 227

页数：4

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