Determination of the thermal conductivity of composite low-k dielectrics for advanced interconnect structures

被引:8
|
作者
Chen, F [1 ]
Gill, J
Harmon, D
Sullivan, T
Strong, A
Li, B
Rathore, H
Edelstein, D
机构
[1] IBM Syst & Technol Grp, Essex Jct, VT 05452 USA
[2] IBM Syst Technol Grp, Fishkill, NY 12533 USA
[3] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA
关键词
D O I
10.1016/j.microrel.2005.05.016
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The increasing use of low-k dielectrics as inter/intralevel insulation materials and the aggressive scaling of advanced interconnects generate new challenges for thermal and electromigration (EM) solutions. Accurate specification of design rules and EM reliability modeling for interconnect systems require knowledge of the thermal behavior of the systems. A key parameter that characterizes thermal behavior is the thermal conductivity of the inter/intralevel dielectric (ILD). In practical, very large scale integration (VLSI) applications, the metal interconnects are fully embedded in a stacked, composite ILD media, which present challenges for the accurate determination of thermal conductivity. This article uses the "effective thermal conductivity" concept to model such complicated composite media, and to introduce a simple methodology that accurately measures effective and bulk thermal conductivities of various thin dielectric layers in integrated circuits (IC). We present measured effective conductivities of several composite media, including various Cu/low-k dielectric configurations: Cu/SiCOH, Cu/spin-on organic dielectric (SOD), Cu/fluorinated silicate glass (FSG), and a hybrid stack with Cu lines in SOD and Cu vias in undoped silicate glass (USG). Recorded temperature measurements ranged from 30 to 120 degrees C using a unique combination of fully embedded Cu lines as heater/thermometers, wafer-level temperature-voltage-power measurements, and the Harmon-Gill (H-G) quasi-analytical heat conduction model. We demonstrated optimal agreement between an experimental method and a finite element simulation, which suggests that this unique technique yields accurate and simple thermal conductivity measurements for complicated systems. Our observations show that thermal conductivities of all films in this study increased with rising substrate temperature. (c) 2005 Elsevier Ltd. All rights reserved.
引用
收藏
页码:232 / 243
页数:12
相关论文
共 50 条
  • [41] Designing porous low-k dielectrics
    Golden, Josh H.
    Hawker, Craig J.
    Ho, Paul S.
    Semiconductor International, 2001, 24 (05) : 79 - 88
  • [42] Plain talk on low-k dielectrics
    Lee, CJ
    Kumar, A
    Ghanbari, A
    SOLID STATE TECHNOLOGY, 2003, 46 (06) : 42 - +
  • [43] Low-k dielectrics for nanoscale MOSFETS
    Raja, P. S.
    Daniel, R. Joseph
    INTERNATIONAL CONFERENCE ON MODELLING OPTIMIZATION AND COMPUTING, 2012, 38 : 2048 - 2052
  • [44] Leakage, breakdown, and TDDB characteristics of porous low-k silica-based interconnect dielectrics
    Ogawa, ET
    Kim, J
    Haase, GS
    Mogul, HC
    McPherson, JW
    41ST ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2003, : 166 - 172
  • [45] Water sorbability of low-k dielectrics measured by thermal desorption spectroscopy
    Yanazawa, H
    Fukuda, T
    Uchida, Y
    Katou, I
    SURFACE SCIENCE, 2004, 566 : 566 - 570
  • [46] Adhesion strength evaluation of low-k interconnect structures using a nanoscratch method
    Ye, JP
    Ueoka, K
    Kojima, N
    Shimanuki, J
    Shimada, N
    Ogawa, S
    MATERIALS, TECHNOLOGY AND RELIABILITY FOR ADVANCED INTERCONNECTS AND LOW-K DIELECTRICS-2004, 2004, 812 : 297 - 302
  • [47] Advanced Cu/Low-k (k=2.2) multilevel interconnect for 0.10/0.07μm generation
    Jang, SM
    Chen, YH
    Chou, TJ
    Lee, SN
    Chen, CC
    Tseng, TC
    Chen, BT
    Chang, SY
    Yu, CH
    Liang, MS
    2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2002, : 18 - 19
  • [48] Thermal conductivity study of porous low-k dielectric materials
    Hu, C
    Morgen, M
    Ho, PS
    Jain, A
    Gill, WN
    Plawsky, JL
    Wayner, PC
    APPLIED PHYSICS LETTERS, 2000, 77 (01) : 145 - 147
  • [49] Interconnect modeling for copper/low-k technologies
    Nagaraj, NS
    Bonifield, T
    Singh, A
    Griesmer, R
    Balsara, P
    17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: DESIGN METHODOLOGIES FOR THE GIGASCALE ERA, 2004, : 425 - 427
  • [50] Cu/Low-k TDDB degradation using ultra low-k (ULK) dielectrics
    Miura, Noriko
    Goto, Kinya
    Hashii, Shinobu
    Suzumura, Naohito
    Miyazaki, Hiroshi
    Matsumoto, Masahiro
    Matsuura, Masazumi
    Asai, Koyu
    ADVANCED METALLIZATION CONFERENCE 2006 (AMC 2006), 2007, : 481 - 487