High resolution focal-plane image processing

Two types of focal plane image processing chips are presented. They address the two extremes of the application spectrum: general purpose and application specific designs. They both exploit the promise of focal-plane computation offered by CMOS technology. The general-purpose computational sensor, a 16 x 16 pixels prototype (easily scalable to larger arrays), has been fabricated in a standard 1.2mu CMOS process, and its spatiotemporal filtering capabilities have been successfully tested. An array larger than 300 x 300 array will use only 0.5% of the chip area for the processing unit while providing multiple spatiotemporally processed images in parallel. The 16 x 16 chip performs I GOPS/mW (5.5-bit scale-accumulate) while computing four spatiotemporal images in parallel. The application specific system realizes a hybrid imaging system by combining a 120 x 36 low-noise active pixel sensor (APS) array with a 60 x 36 current mode motion detection and centroid localization array. These two arrays are spatially interleaved. The APS array, which integrates photo-generated charges on a capacitor in each pixel, includes column parallel correlated double sampling for fixed pattern noise reduction. The current mode array operates in continuous time, however, the programmable motion detection circuit indicates if the intensity of light at pixel is time varying. The centroid, x and y position, of all time varying pixels is computed using circuits located at the edges of the array. Clocked at greater than 60 fps, the chip consumes less than 2mW.