Technical challenges of stencil printing technology for ultra fine pitch flip chip bumping

被引:41
|
作者
Manessis, D
Patzelt, R
Ostmann, A
Aschenbrenner, R
Reichl, H
机构
[1] Tech Univ Berlin, Microperipher Res Ctr, D-13355 Berlin, Germany
[2] Fraunhofer Inst Reliabil & Microintegrat, D-13355 Berlin, Germany
关键词
The authors would like to thank the European Commission for financial support of this work in the framework of CIRRUS Project (IST-1999-10023). The provision of the wafers by the Centre Nacional de Microelectrònica (CNM); Spain is greatly appreciated;
D O I
10.1016/S0026-2714(03)00361-5
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Stencil printing remains the technology route of choice for flip chip bumping because of its economical advantages over traditionally costly evaporation and electroplating processes. This paper provides the first research results on stencil printing of 80 and 60 mum pitch peripheral array configurations with Type 7 Sn63/Pb37 solder paste. In specific, the paste particle size ranges from 2 to 11 mum with an average particle size of 6.5 mum taken into account for aperture packing considerations. Furthermore, the present study unveils the determining role of stencil design and paste characteristics on the final bumping results. The limitations of stencil design are discussed and guidelines for printing improvement are given. Printing of Type 7 solder paste has yielded promising results. Solder bump deposits of 25 and 42 mum have been demonstrated on 80 mum pitch rectangular and round pads, respectively. Stencil printing challenges at 60 mum pitch peripheral arrays are also discussed. (C) 2003 Elsevier Ltd. All rights reserved.
引用
收藏
页码:797 / 803
页数:7
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