Area Efficient Modified Vedic Multiplier

被引：20

作者：

Ram, G. Challa ^{[1
]}

Rani, D. Sudha ^{[1
]}

Lakshmanna, Y. Rama ^{[1
]}

Sindhuri, K. Bala ^{[1
]}

机构：

[1] SRKR Engn Coll, Dept ECE, Bhimavaram, India

来源：

PROCEEDINGS OF IEEE INTERNATIONAL CONFERENCE ON CIRCUIT, POWER AND COMPUTING TECHNOLOGIES (ICCPCT 2016) | 2016年

关键词：

Vedic mathematics; Vedic multiplier; Urdhva-Tiryagbhyam; Array multiplier; Ripple Carry Adder (RCA); Binary to Excess Code Converter (BEC); Half Adder (HA); Full Adder(FA); Carry Select Adder (CSLA);

D O I：

10.1109/ICCPCT.2016.7530294

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

This paper describes the design of high speed Vedic multiplier that uses the techniques of Vedic mathematics based on 16 sutras (algorithms) to improve the performance. In this paper the efficiency of Urdhva Tiryagbhyam (vertical and crosswise) Vedic method for multiplication which is different from the process of normal multiplication is presented. Urdhva -Tiryagbhyam is the most efficient algorithm that gives minimum delay for multiplication for all types of numbers irrespective of their size. Vedic multiplier is coded in Verilog HDL and stimulated and synthesized by using XILINX software 12.2 on Spartan 3E kit. Further the design of array multiplier is compared with the proposed multiplier in terms of delay, memory and power consumption.

引用

页数：5

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