Exploring Design Space of a 3D Stacked Vector Cache

被引：0
|
作者：
Egawa, Ryusuke [1 ]
Endo, Yusuke
Takizwa, Hiroyuki
Kobayashi, Hiroaki [1 ]
Tada, Jubee
机构：
[1] Tohoku Univ, Cybersci Ctr, Sendai, Miyagi 980, Japan
来源：
2012 SC COMPANION: HIGH PERFORMANCE COMPUTING, NETWORKING, STORAGE AND ANALYSIS (SCC) | 2012年
关键词：
component; 3D Die Stacking; TSVs; Vector Cache;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Although 3D integration technologies with through silicon vias (TSVs) have expected to overcome the memory and power wall problems in the future microprocessor design, there is no promising EDA tools to design 3D integrated VLSIs. In addition, effects of 3D integration on microprocessor design have not been discussed well. Under this situation, this paper presents design approach of 3D stacked cache memories using existing EDA tools, and shows early performances evaluation of 3D stacked cache memories for vector processors.
引用
收藏
页码：1475 / +
页数：2
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