Low Area and Low Power Implementation for Competition for Authenticated Encryption, Security, Applicability, and Robustness Authenticated Ciphers

Authenticated Encryption (AE) and Authenticated Encryption with Associated Data (AEAD) play a significant role in cryptography as they simultaneously provide confidentiality, integrity, and authenticity assurances on the data. The Competition for Authenticated Encryption, Security, Applicability, and Robustness (CAESAR) seeks optimal authenticated ciphers based on multiple criteria, including security, performance, area, and energy-efficiency. Low power consumption is one of the main requirements for any chip design targeting the Internet of Things (IoT) applications. In this research paper, low area and low power implementations of selected ciphers from the CAESAR candidates namely NORX, Tiaoxin, SILC, COLM, and JAMBU are provided and Implemented in both Application Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA). For FPGA Implementations a reduction in area with an average of 32% and a reduction in dynamic power with an average of 56% are achieved compared to their corresponding high-speed architectures. While for ASIC Implementations a reduction in area with an average of 36% and a reduction in dynamic power with an average of 43% are achieved compared to their corresponding high-speed architectures. Moreover, throughput (TP) decreases by an average of 70%.