Mapping stresses in high aspect ratio polysilicon electrical through-wafer interconnects

Electrical through-wafer interconnect technologies such as vertical through-silicon vias (TSVs) are essential in order to maximize performance, optimize usage of wafer real estate, and enable three-dimensional packaging in leading edge electronic and microelectromechanical systems (MEMS) products. Although copper TSVs have the advantage of low resistance, highly doped polysilicon TSVs offer designers a much larger range of processing options due to the compatibility of polysilicon with high temperatures and also with the full range of traditional CMOS processes. Large stresses are associated with both Cu and polysilicon TSVs, and their accurate measurement is critical for determining the keep-out zone (KOZ) of transistors and for optimizing downstream processes to maintain high yield. This report presents the fabrication and stress characterization of 400-mu m deep, 20-Omega resistance, high aspect ratio (25: 1) polysilicon TSVs fabricated by deep reactive ion etching (DRIE) followed by low- pressure chemical vapor deposition (LPCVD) of polysilicon with in-situ boron doping. Micro-Raman imaging of the wafer surface showed a maximum stress of 1.2 GPa occurring at the TSV edge and a KOZ of similar to 9 to 11 mu m. For polysilicon TSVs, the stress distribution in the TSVs far from the wafer surface(s) was not previously well- understood due to measurement limitations. Raman spectroscopy was able to overcome this limitation; a TSV cross section was examined and stresses as a function of both depth and width of the TSVs were collected and are analyzed herein. An 1100 degrees C postanneal was found to reduce average stresses by 40%. (C) 2015 Society of Photo-Optical Instrumentation Engineers (SPIE)