Characterization of HfSiAlON/MoAlN PMOSFETs Fabricated by Using a Novel Gate-Last Process

被引：1

作者：

Xu Gao-Bo ^{[1
]}

Xu Qiu-Xia ^{[1
]}

Yin Hua-Xiang ^{[1
]}

Zhou Hua-Jie ^{[1
]}

Yang Tao ^{[1
]}

Niu Jie-Bin ^{[1
]}

He Xiao-Bin ^{[1
]}

Meng Ling-Kuan ^{[1
]}

Yu Jia-Han ^{[1
]}

Li Jun-Feng ^{[1
]}

Yan Jiang ^{[1
]}

Zhao Chao ^{[1
]}

Chen Da-Peng ^{[1
]}

机构：

[1] Chinese Acad Sci, Inst Microelect, Key Lab Microelect Devices & Integrated Technol, Beijing 100029, Peoples R China

来源：

CHINESE PHYSICS LETTERS | 2013年 / 30卷 / 08期

基金：

北京市自然科学基金;

关键词：

LOW-COST; HFSION; DIELECTRICS;

D O I：

10.1088/0256-307X/30/8/087303

中图分类号：

O4 [物理学];

学科分类号：

0702 ;

摘要：

We fabricate p-channel metal-oxide-semiconductor-field-effect-transistors (PMOSFETs) with a HfSiAlON/MoAlN gate stack using a novel and practical gate-last process. In the process, SiO2/poly-Si is adopted as the dummy gate stack and replaced by an HfSiAlON/MoAlN gate stack after source/drain formation. Because of the high-k/metal-gate stack formation after the 1000 degrees C source/drain ion-implant doping activation, the fabricated PMOSFET has good electrical characteristics. The device's saturation driving current is 2.71 x 10(-4) A/mu m (V-GS = V-DS = -1.5 V) and the off-state current is 2.78 x 10(-9) A/mu m. The subthreshold slope of 105 mV/dec (V-DS = -1.5 V), drain induced barrier lowering of 80 mV/V and V-th of -0.3 V are obtained. The research indicates that the present PMOSFET could be a solution for high performance PMOSFET applications.

引用

页数：4

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