coreBIST: A Cellular Automata Based Core for Self Testing System-on-Chips

In this paper, a cellular automata based Built-in self-test (BIST) core design for a self testing System-on-Chip (SoC) is proposed. The objective of the core is to generate pseudo-random test patterns that are injected into the various IP cores within an SoC. The corresponding output patterns are compacted and analyzed for correctness, during the test mode of the SoC. The BIST core was tested on some synthetic SoCs built by integrating ISCAS 85 benchmark circuits. Considerable reduction in the total test time and area is noticed, compared to the corresponding non-BISTEDed SoCs.