Development of a novel deep silicon tapered via etch process for through-silicon interconnection in 3-D integrated systems

被引：14

作者：

Nagarajan, Ranganathan ^{[1
]}

Ebin, Liao ^{[1
]}

Dayong, Lee ^{[2
]}

Seng, Soh Chee ^{[2
]}

Prasad, Krishnamachar ^{[2
]}

Balasubramanian, N. ^{[1
]}

机构：

[1] Inst Microelect, 11 Sci Pk Rd,Singapore Sci Pk 2, Singapore 117685, Singapore

[2] Nanyang Technol Univ, Sch Elect & Elect Engn, Div Microelect, Singapore 639798, Singapore

来源：

56TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE 2006, VOL 1 AND 2, PROCEEDINGS | 2006年

关键词：

D O I：

10.1109/ECTC.2006.1645674

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

A novel dual etch process technology has been demonstrated which provides an opportunity to precisely and independently control the etch throughput and required via slope that is required to achieve conformal deposition of dielectric, copper diffusion barrier and copper seed metallization. It is further shown how a void-free copper via plating has been achieved for implementation into 3-D integrated systems.

引用

页码：383 / +

页数：2

共 50 条

[21] Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits
Savidis, Ioannis
Alam, Syed M.
Jain, Ankur
Pozder, Scott
Jones, Robert E.
Chatterjee, Ritwik
MICROELECTRONICS JOURNAL, 2010, 41 (01) : 9 - 16
[22] Novel Through-Silicon Via Technologies for 3D System Integration
Thadesar, Paragkumar A.
Dembla, Ashish
Brown, Devin
Bakir, Muhannad S.
PROCEEDINGS OF THE 2013 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE (IITC), 2013,
[23] Reliable Via-Middle Copper Through-Silicon Via Technology for 3-D Integration
Beyne, Eric
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2016, 6 (07): : 985 - 994
[24] Coupling Analysis of Through-Silicon Via (TSV) Arrays in Silicon Interposers for 3D Systems
Xie, Biancun
Swaminathan, Madhavan
Han, Ki Jin
Xie, Jianyong
2011 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC), 2011, : 16 - 21
[25] 3-D Integration and Through-Silicon Vias in MEMS and Microsensors
Wang, Zheyao
JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, 2015, 24 (05) : 1211 - 1244
[26] Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs
Lung, Chiao-Ling
Su, Yu-Shih
Huang, Hsih-Hsiu
Shi, Yiyu
Chang, Shih-Chieh
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2013, 32 (07) : 1100 - 1109
[27] Through-Silicon Hole Interposers for 3-D IC Integration
Lau, John H.
Lee, Ching-Kuan
Zhan, Chau-Jie
Wu, Sheng-Tsai
Chao, Yu-Lin
Dai, Ming-Ji
Tain, Ra-Min
Chien, Heng-Chieh
Hung, Jui-Feng
Chien, Chun-Hsien
Cheng, Ren-Shing
Huang, Yu-Wei
Cheng, Yu-Mei
Liao, Li-Ling
Lo, Wei-Chung
Kao, Ming-Jer
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2014, 4 (09): : 1407 - 1419
[28] Through-Silicon via Interconnection for 3D Integration Using Room-Temperature Bonding
Tanaka, Naotaka
Yoshimura, Yasuhiro
Kawashita, Michihiro
Uematsu, Toshihide
Miyazaki, Chuichi
Toma, Norihisa
Hanada, Kenji
Nakanishi, Masaki
Naito, Takahiro
Kikuchi, Takafumi
Akazawa, Takashi
IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2009, 32 (04): : 746 - 753
[29] ROLE OF PROCESS GASES IN MAKING TAPERED THROUGH-SILICON VIAS FOR 3D MEMS PACKAGING
Dixit, Pradeep
Vahanen, Sami
Salonen, Jaakko
Monnoyer, Philippe
2012 7TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT), 2012,
[30] Development of a single step via tapering etch process using deep reactive ion etching with low sidewall roughness for Through-Silicon Via Applications
Praveen, Sampath Kumar
Zain, Muhammad Fariz Mohamed
Xin, Zhang Qing
Johnson, David
PROCEEDINGS OF THE 2012 IEEE 14TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, 2012, : 732 - 735

← 1 2 3 4 5 →