Testability of 123DD based differential pass-transistor logic circuits

Differential Pass-Transistor Logic (DPTL) circuits have demonstrated significant power-delay advantages over conventional CMOS logic circuits. They also offer effective noise immunity by structural means rather than requiring large signal swings. They are particularly suitable for the design of high-speed iterative arithmetic circuits. In this paper we show that DPTL circuits have certain inherent self-checking capabilities. We show that all single transistor faults in a DPTL circuit, either produces the correct output or can be detected by (i)loss of complementarity at the outputs or (ii) excessive current drawn from the power supply. This property can be used to design simple, low-overhead test circuitry that allows fast, on-line detection of single faults. Although detection of all multiple-faults cannot be guaranteed using only the on-line tests, many such faults are also detected by the test circuitry.