Non-synchronous control of bit-serial video signal processor array architectures

被引：0
|
作者：
Riocreux, PA [1 ]
Yates, RB [1 ]
机构：
[1] UNIV SHEFFIELD,DEPT ELECT & ELECT ENGN,ELECT SYST GRP,SHEFFIELD S1 3JD,S YORKSHIRE,ENGLAND
来源：
INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, PROCEEDINGS - VOL II | 1996年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：165 / 168
页数：4
相关论文
共 50 条
  • [21] Towards a high-level synthesis of reconfigurable bit-serial architectures
    Rettberg, A
    Dittmann, H
    Zanella, M
    Lehmann, T
    16TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI 2003, PROCEEDINGS, 2003, : 79 - 84
  • [22] Comparison of bit-serial systolic array implementations of spectral analysers
    Bergmann, N.W.
    National Conference Publication - Institution of Engineers, Australia, 1989, (89 pt 10):
  • [23] A CMOS DESIGN STRATEGY FOR BIT-SERIAL SIGNAL-PROCESSING
    MURRAY, AF
    DENYER, PB
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (03) : 746 - 753
  • [24] A BIT-SERIAL VLSI ARCHITECTURAL METHODOLOGY FOR SIGNAL-PROCESSING
    LYON, RF
    COMPUTER NETWORKS AND ISDN SYSTEMS, 1982, 6 (03): : 228 - 228
  • [25] Towards the implementation of path concepts for a reconfigurable bit-serial synchronous architecture
    Dittmann, Florian
    Rettberg, Achim
    Weber, Raphael
    RECONFIG 2006: PROCEEDINGS OF THE 2006 IEEE INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGA'S, 2006, : 262 - +
  • [26] Bit-serial AOP arithmetic architectures over GF(2m)
    Kim, HS
    Yoo, KY
    INFRASTRUCTURE SECURITY, PROCEEDINGS, 2002, 2437 : 303 - 313
  • [27] A reconfigurable bit-serial VLSI systolic array neuro-chip
    Murtagh, PJ
    Tsoi, AC
    JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 1997, 44 (01) : 53 - 70
  • [28] BIT-SERIAL DIGITAL SIGNAL JITTER CAUSES, EFFECTS, REMEDIES, AND MEASUREMENT
    ROBIN, M
    SMPTE JOURNAL, 1994, 103 (03): : 150 - 156
  • [29] A new approach of a self-timed bit-serial synchronous pipeline architecture
    Rettberg, A
    Zanella, M
    Lehmann, T
    Bobda, C
    14TH IEEE INTERNATIONAL WORKSHOP ON RAPID SYSTEMS PROTOTYPING, PROCEEDINGS: SHORTENING THE PATH FROM SPECIFICATION TO PROTOTYPE, 2003, : 71 - 77
  • [30] A CMOS Imager With a Programmable Bit-Serial Column-Parallel SIMD/MIMD Processor
    Yamashita, Hirofumi
    Sodini, Charles G.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2009, 56 (11) : 2534 - 2545
12345