Fault-Tolerant Mechanisms for Relocation-Aware Dynamic On-Chip Communication on FPGAs

被引：0
|
作者：
Adetomi, Adewale [1 ]
Enemali, Godwin [1 ]
Arslan, Tughrul [1 ]
机构：
[1] Univ Edinburgh, Sch Engn, Inst Integrated Micro & Nano Syst, Edinburgh EH9 3JL, Midlothian, Scotland
来源：
2018 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS (AHS 2018) | 2018年
关键词：
FPGA; CELOC; CERANoC; clock buffers; dynamic communication; network on chip; reliability; relocation;
D O I：
暂无
中图分类号：
V [航空、航天];
学科分类号：
08 ; 0825 ;
摘要：
Fault tolerance has become more important in modern chips. This is because of the increasing use of smaller process nodes. Though there has been a tremendous increase in the integrating density of transistors, the miniaturized size has made them more vulnerable to ageing-and radiation-induced hard errors. In this paper, we present mechanisms for tackling soft and hard errors in CERANoC, a Clock-Enabled Relocation-Aware Network-on-Chip. It has been developed as a communication network that facilitates the online relocation of circuits in response to hard errors. This highlights why it is important that the network itself is resilient to errors.
引用
收藏
页码：214 / 217
页数：4
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