A true block pipelined programmable Reed-Solomon CODEC for high-speed/low-power applications

被引：0

作者：

Kwon, HJ ^{[1
]}

Lee, JS ^{[1
]}

Lee, SH ^{[1
]}

Jeong, BY ^{[1
]}

机构：

[1] Samsung Elect Syst LSI, Soc Dev Team, Yongin, Kyunggi Do, South Korea

来源：

14TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/ASIC.2001.954726

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We propose a Reed-Solomon CODEC architecture. Chip was fabricated using 0.35mum technology. Since it was implemented as a programmable CODEC which can correct upto 16 errors/32 erasures at once, it has versatility regardless of the number of correctable errors and the length of codeword for various applications. Suggested RS-CODEC has "True Block Pipelined Architecture" in which frame latency is equal to the length of codeword leading to maximize throughput to achieve high-speed and low-power at the same time. The input data rate can be amounted to 100MByte per sec.

引用

页码：352 / 355

页数：4

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