An FPGA-Based Acceleration Platform for Auction Algorithm

Auction algorithms have been applied in various linear network problems, such as assignment, transportation, max-flow and shortest path problem. The inherent parallel characteristics of these algorithms are well suited for FPGA hardware implementation. In this paper, we focus on the acceleration of auction algorithm to solve assignment problem. The main contribution is to set up a flexible platform to generate efficient and extendable application-based hardware acceleration. It aims at solving both symmetric and asymmetric assignment problem. Experimental results show that 10X speedup can be achieved using 128 Processing Elements for the problem size of 500.