Design and simulation of hybrid CMOS-SET circuits

被引：24

作者：

Jana, Anindya ^{[1
]}

Singh, N. Basanta ^{[2
]}

Sing, J. K. ^{[3
]}

Sarkar, Subir Kumar ^{[1
]}

机构：

[1] Jadavpur Univ, Dept Elect & Telecommun Engn, Kolkata 700032, India

[2] Manipur Inst Technol, Dept Elect & Commun Engn, Imphal 795004, Manipur, India

[3] Jadavpur Univ, Dept Comp Sci & Engn, Kolkata 700032, India

来源：

MICROELECTRONICS RELIABILITY | 2013年 / 53卷 / 04期

关键词：

MULTIPLE-VALUED LOGIC; SINGLE-ELECTRON; MEMORY;

D O I：

10.1016/j.microrel.2012.11.001

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Single electron devices have extremely poor driving capabilities so that direct application to practical circuits is as yet almost impossible. A new methodology to overcome this problem is to build hybrid circuits consisting of single electron transistors (SETS) and CMOS interfaces. In this work a room temperature operable hybrid CMOS-SET inverter circuit, hybrid CMOS-SET NOR gate and their Voltage Transfer Characteristics (VTCs) are proposed. The MIB compact model for SET device and BSIM4.6.1 model for CMOS are used. The operation of the proposed circuit is verified in Tanner environment. Based on the hybrid CMOS-SET inverter, other logic gates such as NAND, NOR, AND, OR, XOR and XNOR are proposed. All the circuits are verified by means of T-Spice simulation software. (C) 2012 Elsevier Ltd. All rights reserved.

引用

页码：592 / 599

页数：8

共 50 条

[31] Design for diagnosability of CMOS circuits
Wen, XQ
Honzawa, T
Tamamoto, H
Saluja, KK
Kinoshita, K
SEVENTH ASIAN TEST SYMPOSIUM (ATS'98), PROCEEDINGS, 1998, : 144 - 149
[32] Universal test set generation for CMOS circuits
Natl Chiao Tung Univ, Hsinchu, Taiwan
J Electron Test Theory Appl JETTA, 3 (313-323):
[33] A new design technique of hybrid SET/CMOS static memory cells
Lee, BH
Jeong, YH
2003 THIRD IEEE CONFERENCE ON NANOTECHNOLOGY, VOLS ONE AND TWO, PROCEEDINGS, 2003, : 674 - 677
[34] UNIVERSAL TEST SET GENERATION FOR CMOS CIRCUITS
CHEN, BY
LEE, CL
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1995, 6 (03): : 313 - 323
[35] Hybrid Resistor/FET-Logic Demultiplexer Architecture Design for Hybrid CMOS/Nanodevice Circuits
Li, Shu
Zhang, Tong
2007 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, VOLS, 1 AND 2, 2007, : 575 - 580
[36] Hybrid CMOS/molecular electronic circuits
Stan, MR
Rose, GS
Zielger, MM
19TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2005, : 703 - 708
[37] Computing with Hybrid CMOS/STO Circuits
Kabir, Mehdi
Stan, Mircea
2014 51ST ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2014,
[38] Hybrid CMOS/molecular electronic circuits
Stan, Mircea R.
2006 IEEE Conference on Emerging Technologies - Nanoelectronics, 2006, : 183 - 188
[39] A Unified Compact Model for Full-CMOS-Based Hybrid SET-FET Circuits
Singh, Sujit Kumar
Sharma, Deepesh
Dixit, Abhisek
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2025, 72 (01) : 507 - 515
[40] A Comparative Performance Study of Hybrid SET-CMOS Based Logic Circuits for the Estimation of Robustness
Jana, Biswabandhu
Jana, Anindya
Sing, Jamuna Kanta
Sarkar, Subir Kumar
JOURNAL OF NANO- AND ELECTRONIC PHYSICS, 2013, 5 (03)

← 1 2 3 4 5 →