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- [42] Systematic Modeling of On-chip Power Grids with Decaps in TSV-based 3D Chip Integration PROCEEDINGS OF THE 2013 IEEE 15TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2013), 2013, : 575 - 578
- [45] A TSV Repair Scheme Using Enhanced Test Access Architecture for 3-D ICs 2013 22ND ASIAN TEST SYMPOSIUM (ATS), 2013, : 7 - 12
- [47] TSV-based Current Probing Structure using Magnetic Coupling in 2.5D and 3D IC 2015 10TH INTERNATIONAL WORKSHOP ON THE ELECTROMAGNETIC COMPATIBILITY OF INTEGRATED CIRCUITS, 2015, : 212 - 215
- [48] Cost-Effective Test Optimized Scheme of TSV-Based 3D SoCs for Pre-bond Test 2014 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2014, : 209 - 214
- [49] Power Integrity Modeling, Measurement and Analysis of Seven-Chip Stack for TSV-based 3D IC Integration 2015 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC), 2015, : 689 - 692
- [50] BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs 2014 IEEE 23RD ASIAN TEST SYMPOSIUM (ATS), 2014, : 1 - 6