Optimal Design Method for Chip-Area-Efficient CMOS Low-Dropout Regulator

This paper proposes a design method to minimize area of a CMOS low-dropout regulator (LDO) numerically. The new estimation technique for the value of the output voltage ripple under rapid load-current changes is derived, and thus the design procedure to minimize the chip area of the LDO is clarified. To verify the proposed method, the small-area LDO was designed by applying the proposed technique and fabricated in 65nm CMOS process. Measurement result shows the value of the output voltage ripple was suppressed less than 50mV when load current changes from 0 to 30mA in 1 mu s at 1.2V output voltage with 1.8V power supply. And the LDO could be implemented with small chip area of 100 mu m x 100 mu m. The quiescent power consumption was 472 mu W.