共 50 条
- [41] Efficient Test Scheduling for Reusable BIST in 3D Stacked ICs 2017 INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, COMMUNICATIONS AND INFORMATICS (ICACCI), 2017, : 1349 - 1355
- [42] Yield Improvement and Test Cost Optimization for 3D Stacked ICs 2011 20TH ASIAN TEST SYMPOSIUM (ATS), 2011, : 480 - 485
- [43] Test Cost Optimization Technique for the Pre-Bond Test of 3D ICs 2012 IEEE 30TH VLSI TEST SYMPOSIUM (VTS), 2012, : 102 - 107
- [44] Contactless Test Access Mechanism for TSV Based 3D ICs 2013 IEEE 31ST VLSI TEST SYMPOSIUM (VTS), 2013,
- [45] Analysis of Coupling Capacitance Between TSVs and Metal Interconnects in 3D-ICs 2012 19TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2012, : 745 - 748
- [47] A 3D IC BIST for pre-bond test of TSVs using Ring Oscillators 2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 2013,
- [48] Analytical Stress Modeling for TSVs in 3D Packaging 2015 31ST ANNUAL SEMICONDUCTOR THERMAL MEASUREMENT, MODELING & MANAGEMENT SYMPOSIUM (SEMI-THERM), 2015, : 99 - 106
- [49] Challenges in the Reliability of 3D Integration using TSVs 2015 16TH INTERNATIONAL CONFERENCE ON THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICROELECTRONICS AND MICROSYSTEMS (EUROSIME), 2015,
- [50] 3D Floorplanning with Nets-to-TSVs Assignment 2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2014, : 578 - 581