Statistical estimation of correlated leakage power variation and its application to leakage-aware design

Process parameter variations cause large changes in the delay and the leakage power consumption of scaled nanometer CMOS circuits. It has been shown that the layout of a circuit can significantly affect the variation in leakage power by controlling the effect of spatially correlated across-die process variations. In this paper, a method, which efficiently estimates the distribution of leakage power variation caused by correlated process variations, is proposed. The accuracy of the method was validated by comparing the estimated leakage power distribution with Monte Carlo simulation results on ISCAS benchmark circuits. Furthermore, it is shown how the method can be used as a guideline to determine the best possible layout of a circuit.