High-Throughput and High-Speed Polar-Decoder VLSI-Architecture for 5G New Radio

In this paper, we propose a new technique for computing logarithmic-likelihood-ratio (LLR) messages in the processing element (PE) unit of belief-propagation polar decoder that is based on two's complement representation of LLR values. In addition, a new PE-architecture corresponding to this technique has been presented that consumes lesser hardware and has shorter critical-path delay resulting in higher clock-frequency as well as throughput. We have incorporated these PE units in the design of single-column based unidirectional belief-propagation polar-decoder using the round-trip scheduling for decoding the polar code of 1024 code-length and 1/2 code rate. Performance analysis of such decoding algorithm in AWGN channel environment has been carried out and it delivered an adequate bit-error-rate of 10(-4) at 4.2 dB of signal-to-noise ratio. VLSI architecture of the suggested polar-decoder is ASIC synthesized and post-layout simulated in 90 nm and 65 nm CMOS processes using industry standard EDA tools. At 65 nm-CMOS node, our design has achieved a throughput of 11.9 Gbps and a maximum clock frequency of 1.164 GHz. In comparison with the state-of-the-art implementations, our design delivers 10% and 46% better throughput and clock frequency respectively.