Volume and power optimized high-performance system for UAV collision avoidance

被引：0
|
作者：
Nagy, Zoltan [1 ,2 ]
Kiss, Andras [1 ,2 ]
Zarandy, Akos [1 ,2 ]
Zsedrovits, Tamas [2 ]
Vanek, Balint [1 ]
Peni, Tamas [1 ]
Bokor, Jozsef [1 ]
Roska, Tamas [1 ,2 ]
机构：
[1] Hungarian Acad Sci MTA SZTAKI, Comp & Automat Res Inst, Budapest, Hungary
[2] Pazmany Peter Cathol Univ, Fac Informat Technol, Budapest, Hungary
来源：
2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012) | 2012年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An on-board UAV high-performance collision avoidance system sets up drastic constraints, which can be fulfilled by using carefully optimized many-core computational architectures. We report here a case study, where we implemented a many-core processor system, which can process a 100 megapixels/sec video flow, identifying remote airplanes, tracking flying objects by implementing computationally intensive Kalman filters. The introduced processor system is implemented in Spartan 6 FPGA, and consumes less than 1W.
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页码：189 / 192
页数：4
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