Design of ADPLL System for WiMAX Applications in 40-nm CMOS

被引：0

作者：

Jiang, Wenlong ^{[1
,3
]}

Tavakol, Armin ^{[1
]}

Effendrik, Popong ^{[1
]}

van de Gevel, Marcel ^{[2
]}

Verwaal, Frank ^{[2
]}

Staszewski, R. Bogdan ^{[1
]}

机构：

[1] Delft Univ Technol, NL-2628 CD Delft, Netherlands

[2] Catena Microelect BV, NL-2628 XG Delft, Netherlands

[3] Univ Calif Los Angeles, Los Angeles, CA 90024 USA

来源：

2012 19TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS) | 2012年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present an all-digital phase-locked loop (ADPLL)-based frequency synthesizer for WiMAX applications implemented in 40-nm CMOS. Via frequency planning and design of multiple capacitor-banks in a digitally-controlled oscillator (DCO), the ADPLL covers dual bands of 2.3-2.7 GHz and 3.3-3.8 GHz, while achieving a fine frequency resolution of 25 Hz. The time-to-digital converter (TDC) achieves a resolution of better than 13 ps. Several techniques have been proposed to improve system performance. The whole system is simulated via Verilog-AMS with digital circuits at the gate level. The ADPLL achieves an integrated phase noise of better than -40 dBc from 1 kHz to 10 MHz, and settling time is within 15 us.

引用

页码：73 / 76

页数：4

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