Design of ADPLL System for WiMAX Applications in 40-nm CMOS

We present an all-digital phase-locked loop (ADPLL)-based frequency synthesizer for WiMAX applications implemented in 40-nm CMOS. Via frequency planning and design of multiple capacitor-banks in a digitally-controlled oscillator (DCO), the ADPLL covers dual bands of 2.3-2.7 GHz and 3.3-3.8 GHz, while achieving a fine frequency resolution of 25 Hz. The time-to-digital converter (TDC) achieves a resolution of better than 13 ps. Several techniques have been proposed to improve system performance. The whole system is simulated via Verilog-AMS with digital circuits at the gate level. The ADPLL achieves an integrated phase noise of better than -40 dBc from 1 kHz to 10 MHz, and settling time is within 15 us.