A single chip motion JPEG codec LSI

被引：11

作者：

Okada, S ^{[1
]}

Matsuda, Y ^{[1
]}

Watanabe, T ^{[1
]}

Kondo, K ^{[1
]}

机构：

[1] SANYO ELECT CO LTD,MOS LSI DIV,GIFU 50301,JAPAN

来源：

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS | 1997年 / 43卷 / 03期

关键词：

D O I：

10.1109/30.628651

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have developed a single chip motion JPEG codec LSI that can compress and decompress VGA-size (640 pixels x 480 lines) JPEG images at the rate of 30 frames per second simply by connecting a single external buffer memory chip. The LSI can control compression ratio control technique to store a fixed number of images when there is limited memory capacity, and it compresses data stored in the frame buffer to enable high-speed signal processing without the use of high-speed image memory. The JPEG codec core is small (40,000 gates) and power consumption is low (220 mW), making it well suited to a wide range of image processing applications in consumer products.

引用

页码：418 / 422

页数：5

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