Seeking Low-Power Synchronous/Asynchronous Systems: A FIR Implementation Case Study

被引:0
|
作者
Skaf, Ali [1 ]
Simatic, Jean [2 ,3 ]
Fesquet, Laurent [2 ,3 ]
机构
[1] Syrian Private Univ, Damascus, Syria
[2] Univ Grenoble Alpes, TIMA Lab, F-38031 Grenoble, France
[3] CNRS, TIMA Lab, F-38031 Grenoble, France
关键词
low-power embedded systems; IoT; optimized synchronous design; event-driven sampling; asynchronous circuits;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Seeking low-power consumption high-performance embedded systems has been at the center of interest for researchers around the world for the last decades, especially with the recent boom of different hand-held battery-operated mobile connected devices. The new trends and needs of faster, smarter and smaller internet connected systems, also known as the IoT, require developing very-low power embedded systems including actuators, sensors and signal processors. In this paper, we focus on the architecture optimization efforts to reduce the required activity using the FIR filter as a demonstration example. The new optimized implementation of the FIR filter was compared with other synchronous and asynchronous FIR filter versions realized using the ALPS framework developed at TIMA laboratory. The obtained FIR architecture exhibits 43% less area and up to 61% power consumption reduction compared to the best previous synchronous implementation. We plan to use these results to improve the automatically generated datapath of the high-level synthesis tool of our framework (ALPS-HLS).
引用
收藏
页码:581 / 584
页数:4
相关论文
共 50 条
  • [31] Low-power and area-efficient FIR filter implementation suitable for multiple taps
    Kim, KS
    Lee, K
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2003, 11 (01) : 150 - 153
  • [32] Evolutionary Techniques for Precise and Real-Time Implementation of Low-Power FIR Filters
    Stefatos, Evangelos F.
    Arslan, Tughrul
    Hamilton, Alister
    2008 IEEE CONGRESS ON EVOLUTIONARY COMPUTATION, VOLS 1-8, 2008, : 2701 - +
  • [33] A New Low-Power Architecture Design for Distributed Arithmetic Unit in FIR Filter Implementation
    Seyedeh Fatemeh Ghamkhari
    Mohammad Bagher Ghaznavi-Ghoushchi
    Circuits, Systems, and Signal Processing, 2014, 33 : 1245 - 1259
  • [34] A New Low-Power Architecture Design for Distributed Arithmetic Unit in FIR Filter Implementation
    Ghamkhari, Seyedeh Fatemeh
    Ghaznavi-Ghoushchi, Mohammad Bagher
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2014, 33 (04) : 1245 - 1259
  • [35] A low-power folded programmable FIR architecture
    Chen, Li-Hsun
    Chen, Oscal T. -C.
    2006 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS DESIGN AND IMPLEMENTATION, 2006, : 188 - 193
  • [36] Low-power synchronous-to-asynchronous-to-synchronous interlocked, pipelined CMOS circuits operating at 3.3-4.5 GHz
    Schuster, SE
    Cook, PW
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (04) : 622 - 630
  • [37] Exploiting Sparse Activation for Low-Power Design of Synchronous Neuromorphic Systems
    Chung, Jaeyong
    Kang, Woochul
    IEICE TRANSACTIONS ON ELECTRONICS, 2017, E100C (11) : 1073 - 1076
  • [38] An asynchronous Viterbi Decoder for low-power applications
    Javadi, B
    Naderi, M
    Pedram, H
    Afzali-Kusha, A
    Akbari, MK
    INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2003, 2799 : 471 - 480
  • [39] Design and implementation of low-power IIR digital filter systems
    Saab, S
    Lu, WS
    Antoniou, A
    ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 3: ANALOG AND DIGITAL SIGNAL PROCESSING, 1999, : 391 - 394
  • [40] Design of asynchronous pipelines for low-power microprocessor
    Shi, Wei
    Wang, You-Rui
    Chen, Fang-Yuan
    Ren, Hong-Guang
    Lu, Hong-Yi
    Wang, Zhi-Ying
    Guofang Keji Daxue Xuebao/Journal of National University of Defense Technology, 2009, 31 (05): : 33 - 37