Power Analysis for Asynchronous Network-on-Chip

被引：0

作者：

Abd El Ghany, Mohamed A. ^{[1
,2
]}

Reehal, Gursharan ^{[3
]}

Ismail, Mohammed ^{[4
]}

机构：

[1] German Univ Cairo, Dept Elect Engn, Cairo, Egypt

[2] Tech Univ Darmstadt, Dept Elect Engn & Informat Technol, Darmstadt, Germany

[3] Ohio State Univ, Dept Elect & Comp Engn, Columbus, OH 43210 USA

[4] Ohio State Univ, Columbus, OH 43210 USA

来源：

IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING | 2013年 / 8卷

关键词：

NoC; GALS; low power; power analysis; INTERCONNECT; INTERFACES;

D O I：

10.1002/tee.21921

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An asynchronous architecture is proposed to achieve a low-power network-on-chip (NoC). The area of the asynchronous switch is increased by 25% as compared to the synchronous switch. However, the power dissipation of the asynchronous architecture could be decreased by up to 55%. Even though clock gating is used, the asynchronous design achieves significant power reduction of 28%. The total metal resource required to implement the asynchronous design is decreased by up to 12%. As technology advances and network density increases, the reduction in power dissipation reaches 22% for 256 IPs with the same chip size. The asynchronous butterfly fat tree (BFT) architecture dissipates the minimum power as compared to other NoC topologies. (c) 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

引用

页码：S72 / S80

页数：9

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