Power Analysis for Asynchronous Network-on-Chip

被引：0

作者：

Abd El Ghany, Mohamed A. ^{[1
,2
]}

Reehal, Gursharan ^{[3
]}

Ismail, Mohammed ^{[4
]}

机构：

[1] German Univ Cairo, Dept Elect Engn, Cairo, Egypt

[2] Tech Univ Darmstadt, Dept Elect Engn & Informat Technol, Darmstadt, Germany

[3] Ohio State Univ, Dept Elect & Comp Engn, Columbus, OH 43210 USA

[4] Ohio State Univ, Columbus, OH 43210 USA

来源：

IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING | 2013年 / 8卷

关键词：

NoC; GALS; low power; power analysis; INTERCONNECT; INTERFACES;

D O I：

10.1002/tee.21921

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An asynchronous architecture is proposed to achieve a low-power network-on-chip (NoC). The area of the asynchronous switch is increased by 25% as compared to the synchronous switch. However, the power dissipation of the asynchronous architecture could be decreased by up to 55%. Even though clock gating is used, the asynchronous design achieves significant power reduction of 28%. The total metal resource required to implement the asynchronous design is decreased by up to 12%. As technology advances and network density increases, the reduction in power dissipation reaches 22% for 256 IPs with the same chip size. The asynchronous butterfly fat tree (BFT) architecture dissipates the minimum power as compared to other NoC topologies. (c) 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

引用

页码：S72 / S80

页数：9

共 50 条

[31] Intelligent computation techniques for optimization of the shortest path in an asynchronous network-on-chip
K. Ilamathi
P. Rangarajan
Cluster Computing, 2019, 22 : 335 - 346
[32] Formal verification of CHP specifications with CADP illustration on an asynchronous network-on-chip
Salaun, Gwen
Serwe, Wendelin
Thonnart, Yvain
Vivet, Pascal
ASYNC 2007: 13TH IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS, 2007, : 73 - +
[33] Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey
Asadi, Bahareh
Zia, Syed Maqsood
Al-Khafaji, Hamza Mohammed Ridha
Mohamadian, Asghar
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2023, 39 (01): : 11 - 25
[34] Synthesis and Layout of an Asynchronous Network-on-Chip using Standard EDA Tools
Muller, Christoph Thomas
Kasapaki, Evangelia
Sorensen, Rasmus Bo
Sparso, Jens
2014 NORCHIP, 2014,
[35] Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey
Bahareh Asadi
Syed Maqsood Zia
Hamza Mohammed Ridha Al-Khafaji
Asghar Mohamadian
Journal of Electronic Testing, 2023, 39 : 11 - 25
[36] A Power, Thermal and Reliability-Aware Network-on-Chip
Sharma, Ashish
Gupta, Yogendra
Yadav, Sonal
Bhargava, Lava
Gaur, Manoj Singh
Laxmi, Vijay
2017 3RD IEEE INTERNATIONAL SYMPOSIUM ON NANOELECTRONIC AND INFORMATION SYSTEMS (INIS), 2017, : 243 - 245
[37] Power-gating technique for network-on-chip buffers
Casu, M. R.
Yadav, M. K.
Zamboni, M.
ELECTRONICS LETTERS, 2013, 49 (23) : 1438 - 1440
[38] An Accurate Power and Temperature Simulation Framework for Network-on-Chip
Yang, Jianxun
Cao, Shan
PROCEEDINGS OF 2016 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS AND MICROSYSTEMS (ICICM), 2016, : 166 - 171
[39] Power Efficient Photonic Network-on-Chip for a Scalable GPU
Bashir, Janibul
Sethi, Khushal
Sarangi, Smruti R.
PROCEEDINGS OF THE 13TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS'19), 2019,
[40] QuT: A Low-Power Optical Network-on-Chip
Hamedani, Parisa Khadem
Jerger, Natalie Enright
Hessabi, Shaahin
2014 EIGHTH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS), 2014, : 80 - 87

← 1 2 3 4 5 →