A New Hardware Accelerator for Data Sorting in Area & Energy Constrained Architectures

Sorting is one of the most important computational tasks in data processing applications. Recent studies show that the FPGA-based hardware accelerators are more efficient than the general-purpose processors and GPUs. By increasing the input records in the sorting network, the number of Compare-And-Swap (CAS) units would be increased, which in turn, will lead to increased resource consumption. In some applications, the number of available resources is limited. Thereby, it is necessary to optimize resource requirements while maintaining a sufficient level of performance. This paper presents a new sorting architecture that reduces the number of required resources compared to the state-of-the-art sorting architecture and achieves the desired performance using Unary processing. Results indicate that the proposed architecture increases throughput by 29.1% and reduces the number of LUTs by 42%, for sorting 8-input records, compared to other architecture.