Design and Implementation of a Power and Speed Efficient Carry Select Adder on FPGA

被引：0
|
作者：
Chawla, Simarpreet Singh [1 ]
Aggarwal, Swapnil [1 ]
Goel, Nidhi [1 ]
Bhatia, Mantek Singh [2 ]
机构：
[1] Delhi Technol Univ, Dept Elect & Commun Engn, Delhi, India
[2] Amity Univ, Dept Comp Sci & Technol, Noida, India
来源：
PROCEEDINGS OF THE 10TH INDIACOM - 2016 3RD INTERNATIONAL CONFERENCE ON COMPUTING FOR SUSTAINABLE GLOBAL DEVELOPMENT | 2016年
关键词：
Carry Look Ahead Adder (CLAA); Carry Select Adder (CSA); Arithmetic and Logic Unit (ALU); Multiplexer (MUX);
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
Adders are one of the most common unit in digital systems. The speed, power and area occupied by an adder play a vital role in Digital Signal Processing system, Image Processing system, etc. Hence, they play an important role in deciding the time period of the clock, the place and route of various units comprising of the system and total power consumed by the system. In this paper, we propose a new architecture for a modified sequential high speed carry select adder. We have given emphasis on optimizing the time period of the clock and power consumed, by using the carry ahead generation technique of Carry Look Ahead Adder (CLAA) and multiplexing technique of Carry Select Adder (CSA). The proposed CSA was implemented on Virtex-7 and results were calculated using Vivado Design Suite 2014.4.
引用
收藏
页码：571 / 576
页数：6
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