Automated Correction of Design Errors by Edge Redirection on High-Level Decision Diagrams

被引:0
|
作者
Karputkin, Anton [1 ]
Ubar, Raimund [1 ]
Tombak, Mati [1 ]
Raik, Jaan [1 ]
机构
[1] Tallinn Univ Technol, Tallinn, Estonia
关键词
high level decision diagrams; equivalence checking; automated error correction;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The paper presents a new method for design error correction by edge redirection on High-Level Decision Diagrams (HLDDs). In this paper, a canonical form of HLDDs developed by the authors is applied to automated correction of design errors. We show how realistic design errors can be represented by the redirection-based fault model. The theoretical basis of the approach is presented with the key advantages being the ability to handle multiple errors as well as the fact that the error correction is not restricted by the input stimuli. The method has been evaluated on a set of ITC99 benchmarks and on three real-world cores. Experiments show that the method is capable of correcting multiple design errors in very short run times
引用
收藏
页码:686 / 693
页数:8
相关论文
共 50 条
  • [21] HIGH-LEVEL DESIGN
    BOURBON, BR
    COMPUTER DESIGN, 1992, 31 (09): : 27 - 29
  • [22] High-Level Decision Making for Automated Highway Driving via Behavior Cloning
    Wang, Lingguang
    Fernandez, Carlos
    Stiller, Christoph
    IEEE TRANSACTIONS ON INTELLIGENT VEHICLES, 2023, 8 (01): : 923 - 935
  • [23] A methodology and tool for automated transformational high-level design space exploration
    Gerlach, J
    Rosenstiel, W
    2000 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS, 2000, : 545 - 548
  • [24] On the Use of Artificial Neural Networks for the Automated High-Level Design of ΣΔ Modulators
    Diaz-Lobo, Pablo
    Linan-Cembrano, Gustavo
    de la Rosa, Jose M.
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2024, 71 (05) : 2006 - 2016
  • [25] Software-based self-test generation for microprocessors with high-level decision diagrams
    Jasnetski, Artjom
    Ubar, Raimund
    Tsertov, Anton
    Brik, Marina
    PROCEEDINGS OF THE ESTONIAN ACADEMY OF SCIENCES, 2014, 63 (01) : 48 - 61
  • [26] Software-based Self-Test Generation for Microprocessors with High-Level Decision Diagrams
    Ubar, Raimund
    Tsertov, Anton
    Jasnetski, Artjom
    Brik, Marina
    2014 15TH LATIN AMERICAN TEST WORKSHOP - LATW, 2014,
  • [27] Back-tracing and event-driven techniques in high-level simulation with decision diagrams
    Ubar, R
    Raik, J
    Morawiec, A
    ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL I: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY, 2000, : 208 - 211
  • [28] THE FUTURE OF HIGH-LEVEL DESIGN
    DEGEUS, AJ
    ELECTRONIC DESIGN, 1992, 40 (24) : 122 - 122
  • [29] HIGH-LEVEL LANGUAGE DESIGN
    ALLWEISS, JA
    MCCLINTOCK, JH
    DATAMATION, 1981, 27 (04): : 186 - &
  • [30] HIGH-LEVEL DESIGN ISSUES
    SHELDON, C
    ELECTRONIC ENGINEERING, 1994, 66 (807): : 12 - 12