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- [14] Multiple Fault Testing in Systems-on-Chip with High-Level Decision Diagrams 2015 10TH INTERNATIONAL DESIGN & TEST SYMPOSIUM (IDT), 2015, : 66 - 71
- [15] Application of high-level decision diagrams for simulation-based verification tasks Estonian Journal of Engineering, 2010, 16 (01): : 56 - 77
- [16] PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2009, 25 (06): : 289 - 300
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- [19] High-level FSMD design and automated clock gating with CoDeL CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUE, 2008, 33 (01): : 31 - 38
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