A low-power and high-speed D flip-flop using a single latch

被引：1

作者：

Chang, RC ^{[1
]}

Hsu, LC ^{[1
]}

Sun, MC ^{[1
]}

机构：

[1] Natl Chunghsing Univ, Dept Elect Engn, Taichung 40227, Taiwan

来源：

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS | 2002年 / 11卷 / 01期

关键词：

D O I：

10.1142/S0218126602000239

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse, Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

引用

页码：51 / 55

页数：5

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