A low-power direct digital frequency synthesizer architecture for wireless communications

被引：6
|
作者：
Bellaouar, A [1 ]
Obrecht, M [1 ]
Fahim, A [1 ]
Elmasry, MI [1 ]
机构：
[1] Univ Waterloo, VLSI Res Grp, Waterloo, ON N2L 3G1, Canada
来源：
PROCEEDINGS OF THE IEEE 1999 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 1999年
关键词：
D O I：
10.1109/CICC.1999.777351
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A novel low-power direct digital frequency synthesizer (DDFS) architecture is presented. The sine and cosine functions are generated by linearly interpolating between the sample points, reducing the size of the ROM look-up table to 416 bits for 9-bit output resolution. The DDFS is implemented in 0.8 mu m CMOS technology and features 60dBc spectral purity, 48 Hz frequency resolution, with only 9.5mW (@30MHz, 3.3V) power dissipation.
引用
收藏
页码：593 / 596
页数：4
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