A low-power CMOS frequency synthesizer for GPS receivers

被引：4

作者：

于云丰 ^{[1
]}

乐建连 ^{[2
]}

肖时茂 ^{[1
]}

庄海孝 ^{[1
]}

马成炎 ^{[1
,2
]}

叶甜春 ^{[1
]}

机构：

[1] Institute of Microelectronics Chinese Academy of Sciences

[2] Hangzhou Zhongke Microelectronics Co.Ltd.

来源：

半导体学报 | 2010年 / 06期

基金：

国家高技术研究发展计划(863计划);

关键词：

frequency synthesizer; GPS; CMOS; PLL; source-coupled logic; prescaler;

D O I：

暂无

中图分类号：

TN74 [频率合成技术、频率合成器]; TN967.1 [卫星导航系统];

学科分类号：

摘要：

A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18μm CMOS process is introduced.By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time,the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscillator signals has been increased,compared with traditional prescalers.Measurement results show that this synthesizer achieves an in-band phase noise of-87 dBc/Hz at 15 kHz offset,with spurs less than-65 dBc.The whole synthesizer consumes 6 mA in the case of a 1.8 V supply,and its core area is 0.6 mm;.

引用

页码：139 / 143

页数：5

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