Power Clock Generator design Using Delay Locked Loop For Adiabatic Logic

Adiabatic circuits operate with low power consumption due to the retrieval of charge stored in the load capacitances of the circuits. The circuits are becoming a promising alternative to Bulk CMOS electronic circuits. The adiabatic logic families use CLOCK as power supply to the circuits whereas Bulk CMOS Circuits use constant voltage source. This paper presents an implementation of a power clock generator using delay locked loop for adiabatic circuit. The paper presents the detail implementation issues in the power clock generator design. The proposed design uses a Phase combiner which generates the power clock of frequency greater than 1 GHz. The extended version using FinFET based architecture will be proposed in future. The simulations are carried out in HSPICE using predictive technology models in 32nm.