A low-cost BIST scheme for ADC testing

被引:0
|
作者
Wang, YS [1 ]
Wang, JX [1 ]
Lai, FC [1 ]
Ye, YZ [1 ]
机构
[1] Harbin Inst Technol, Ctr Microelect, Harbin 150001, Heilongjiang, Peoples R China
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A low-cost BIST scheme based on linear histogram for testing ADC is presented in this paper. A parallel time decomposition technique is presented to minimize not only hardware overhead but also testing time of the BIST scheme based on histogram. An area-efficient linear triangular waveform generator is discussed as test stimulus. The technique uses digital delta-sigma noise shaping to generate the on-chip precise analog stimulus and simplify the analog circuit of the generator at same time. A practical implementation is described and the performance is evaluated.
引用
收藏
页码:665 / 668
页数:4
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