Multi-Histogram ADC BIST System for ADC Linearity Testing

被引：4
|
作者：
Chan, Koay Soon [1 ]
Nordin, Nuzrul Fahmi [1 ]
Chan, Kim Chon [1 ]
Lok, Terk Zyou [1 ]
Yong, Chee Wai [1 ]
机构：
[1] Marvell Semicond Sdn Bhd, George Town, Malaysia
来源：
2013 22ND ASIAN TEST SYMPOSIUM (ATS) | 2013年
关键词：
Built-in Self-test; ADC BIST; ADC linearity test; Histogram testing; Triangle wave;
D O I：
10.1109/ATS.2013.47
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes an ADC BIST system that utilizes a modified linear ramp histogram approach to test the linearity of an ADC with 10 bits of resolution on a System-On-Chip (SoC). The system tests the differential non-linearity (DNL) and Integral Non-linearity (INL) of an ADC. The ADC is tested in sections using a small amplitude triangle wave which is generated by charging and discharging an on-chip capacitor. This is an alternative solution to test an ADC when ADC-DAC loopback testing is not feasible. Both the ADC and BIST are designed in the 40nm process node. Simulation results show that the BIST is capable of testing a 10-bit ADC.
引用
收藏
页码：213 / 214
页数：2
相关论文
共 50 条
  • [1] A complete BIST scheme for ADC linearity testing
    Wu, GL
    Ling, M
    Rao, J
    Shi, LX
    2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS, 2004, : 2051 - 2054
  • [2] A Novel Linear Histogram BIST for ADC
    Ren, Jianguo
    Feng, Jianhua
    Ye, Hongfei
    2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 2091 - 2094
  • [3] A fully digital-compatible BIST strategy for ADC linearity testing
    Xing, Hanqing
    Jiang, Hanjun
    Chen, Degang
    Geiger, Randall
    2007 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, 2007, : 884 - +
  • [4] A SAR ADC BIST for Simplified Linearity Test
    Chao, An-Sheng
    Chang, Soon-Jyh
    Ting, Hsin-Wen
    2011 IEEE INTERNATIONAL SOC CONFERENCE (SOCC), 2011, : 146 - 149
  • [5] Optimal schemes for ADC BIST based on histogram
    Wang, YS
    Wang, JX
    Lai, FC
    Ye, YZ
    14TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2005, : 52 - 57
  • [6] SNR Measurement Based on Linearity Test for ADC BIST
    Duan, Jingbo
    Chen, Degang
    2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 269 - 272
  • [7] Analog BIST generator for ADC testing
    Bernard, S
    Azaïs, F
    Bertrand, Y
    Renovell, M
    2001 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2001, : 338 - 346
  • [8] Embedded ADC characterization techniques using a BIST structure, an ADC model and histogram data
    Raczkowycz, J
    Allott, S
    MICROELECTRONICS JOURNAL, 1996, 27 (06) : 539 - 549
  • [9] Combining the Histogram Method and the Ultrafast Segmented Model Identification of Linearity Errors Algorithm for ADC Linearity Testing
    Chen, Weida
    Zhu, Yongxin
    Liu, Xinyi
    Li, Xinyang
    Ou, Dongyu
    2016 21TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), 2016,
  • [10] Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST
    F. Azaïs
    S. Bernard
    Y. Bertrand
    M. Renovell
    Journal of Electronic Testing, 2001, 17 : 255 - 266
12345