Computationally Efficient Analytic Charge Model for III-V Cylindrical Nanowire Transistors

被引：0
|
作者：
Ganeriwala, Mohit D. [1 ]
Marin, Enrique G. [2 ,3 ]
Ruiz, Francisco G. [2 ,3 ]
Mohapatra, Nihar R. [1 ]
机构：
[1] Indian Inst Technol, Dept Elect Engn, Gandhinagar, India
[2] Univ Pisa, Dept Informat Engn, Pisa, Italy
[3] Univ Granada, Dept Elect, Granada, Spain
来源：
2018 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS) | 2018年
关键词：
CAPACITANCE; SILICON;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, we present a computationally efficient compact model for calculating the charges and gate capacitance of III-V cylindrical nanowire transistors. We proposed an approximation which decouples the Poisson and the Schrodinger equation and addresses the issues of developing a computationally efficient analytical model. Using the proposed approximation, we derived a model suitable for the circuit simulators. The model is physics based and does not include any empirical parameters. The accuracy of the model is verified across nanowires of different sizes and materials using simulation results from a 2D Poisson-Schrodinger solver.
引用
收藏
页码：193 / 195
页数：3
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