Compressor design for silicon debug

被引：0
|
作者：
Zhang, Jing [1 ]
Fritz, Lars Johan [2 ]
Liu, Liang [1 ]
Larsson, Erik [1 ]
机构：
[1] Lund Univ, Dept Elect & Informat Technol, S-22100 Lund, Sweden
[2] Ericsson, Stockholm, Sweden
来源：
2016 21TH IEEE EUROPEAN TEST SYMPOSIUM (ETS) | 2016年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The objective of this paper is to design a compressor for silicon debug that is suitable in an industrial Nexus environment. The compressor must operate in real-time and must be lossless. Important for the compressor is high compression ratio, low hardware cost and high throughput. We implemented the compression on an FPGA and we compared our implementation in terms of throughput and hardware cost against other approaches.
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页数：2
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