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- [41] Residual Stress Effect of Copper-Filled Through Silicon Via on Performances of Nano-Scaled Devices in 3D-ICs Interposer 2015 10TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT), 2015, : 250 - 253
- [42] Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps 58TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, PROCEEDINGS, 2008, : 1073 - 1081
- [43] Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2009, 32 (04): : 720 - 728
- [44] Investigation of the Fabrication Parameters' Influence on the Tensile Strength of 3D-Printed Copper-Filled Metal Composite Using Design of Experiments JOURNAL OF MANUFACTURING AND MATERIALS PROCESSING, 2024, 8 (06):
- [46] Thermo-mechanical Reliability of Copper-filled and Polymer-filled Through Silicon Vias in 3D Interconnects 2013 IEEE 63RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2013, : 2132 - 2137
- [47] Numerical simulation of electro-migration failure of copper-filled via holes in ULSI interconnects NINETEENTH ANNUAL IEEE SEMICONDUCTOR THERMAL MEASUREMENT AND MANAGEMENT SYMPOSIUM, 2003, : 210 - 214
- [48] Si interposer with high aspect ratio copper filled TSV for system integration 2015 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE AND 2015 IEEE MATERIALS FOR ADVANCED METALLIZATION CONFERENCE (IITC/MAM), 2015, : 245 - 247
- [50] Reduction of Thermal Stress in Copper TSV due to Annealing by Low TEC Copper MATERIALS, FORMULATION, AND PROCESSES FOR SEMICONDUCTOR, 2.5 AND 3D CHIP PACKAGING, AND HIGH DENSITY INTERCONNECTION PCB, 2018, 86 (08): : 17 - 21