A Trapezoidal Cross-Section Stacked Gate FinFET with Gate Extension for Improved Gate Control

被引:0
|
作者
Mangesh, Sangeeta [1 ]
Chopra, Pradeep [2 ]
Saini, Krishan K. [3 ]
机构
[1] Dr APJ Abdul Kalam Tech Univ Lucknow, Lucknow, Uttar Pradesh, India
[2] Ajay Kumar Garg Engn Coll, Dept ECE, Ghaziabad, India
[3] Natl Phys Labs, New Delhi, India
关键词
Drain Induced Barrier Lowering (DIBL); Gate Induced Drain Leakage (GIDL); Subthreshold Swing (SS); Silicon On-Insulator (SOI);
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
An improved trapezoidal pile gate bulk FinFET device is implemented with an extension in the gate for enhancing the performance. The novelty in the design is trapezoidal cross-section FinFET with stacked metal gate along with extension on both sides. Such improved device structure with additional process cost exhibits significant enhancement in the performance metrics specially in terms of leakage current behavior. The simulation study proves the suitability of the device for low power applications with improved on/off current ratio, subthreshold swing (SS), drain induced barrier lowering (DIBL), Gate Induced Drain Leakage (GIDL) uniform distribution of electron charge density along the channel and effects of Augur recombination within the channel.
引用
收藏
页码:189 / 194
页数:6
相关论文
共 50 条
  • [41] TCAD Temperature Analysis of Gate Stack Gate All Around (GS-GAA) FinFET for Improved RF and Wireless Performance
    Bhavya Kumar
    Rishu Chaujar
    Silicon, 2021, 13 : 3741 - 3753
  • [42] Gate oxide integrity(GOI) of MOS transistors with W/TiN stacked gate
    Lee, DH
    Yeom, KH
    Cho, MH
    Kang, NS
    Shim, TE
    1996 SYMPOSIUM ON VLSI TECHNOLOGY: DIGEST OF TECHNICAL PAPERS, 1996, : 208 - 209
  • [43] TCAD Temperature Analysis of Gate Stack Gate All Around (GS-GAA) FinFET for Improved RF and Wireless Performance
    Kumar, Bhavya
    Chaujar, Rishu
    SILICON, 2021, 13 (10) : 3741 - 3753
  • [44] Polarity Control in Double-Gate, Gate-All-Around Vertically Stacked Silicon Nanowire FETs
    De Marchi, M.
    Sacchetto, D.
    Frache, S.
    Zhang, J.
    Gaillardon, P. -E.
    Leblebici, Y.
    De Micheli, G.
    2012 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2012,
  • [45] THE CONSTANCY EFFECT OF THE FLOW-RATE THROUGH THE REDUCED OUTLET CROSS-SECTION OF THE GATE RUNNERS
    NIKITIN, VG
    DOKLADY AKADEMII NAUK BELARUSI, 1988, 32 (01): : 32 - 35
  • [46] A Dual Gate Junctionless FinFET for Biosensing Applications
    Umamaheshwar Soma
    Silicon, 2022, 14 : 8881 - 8885
  • [47] STACKED OXIDE AS TRENCH GATE DIELECTRIC
    TSOU, LY
    KUO, DS
    EGLOFF, RH
    MUKHERJEE, S
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY A-VACUUM SURFACES AND FILMS, 1992, 10 (04): : 728 - 732
  • [48] Improved surface-roughness scattering and mobility models for multi-gate FETs with arbitrary cross-section and biasing scheme
    Lizzit, D.
    Badami, O.
    Specogna, R.
    Esseni, D.
    JOURNAL OF APPLIED PHYSICS, 2017, 121 (24)
  • [49] ANALYSIS OF FINFET CHARACTERISTICS WITH GATE LENGTH SCALLING
    Sustkova, Hana
    Voves, Jan
    NANOCON 2014, 6TH INTERNATIONAL CONFERENCE, 2015, : 814 - 819
  • [50] CHALLENGES AND SOLUTIONS TO FINFET GATE ETCH PROCESS
    Han, Qiu-Hua
    Meng, Xiao-Ying
    Zhang, Hai-Yang
    2015 China Semiconductor Technology International Conference, 2015,