A Trapezoidal Cross-Section Stacked Gate FinFET with Gate Extension for Improved Gate Control

被引：0
|
作者：
Mangesh, Sangeeta [1 ]
Chopra, Pradeep [2 ]
Saini, Krishan K. [3 ]
机构：
[1] Dr APJ Abdul Kalam Tech Univ Lucknow, Lucknow, Uttar Pradesh, India
[2] Ajay Kumar Garg Engn Coll, Dept ECE, Ghaziabad, India
[3] Natl Phys Labs, New Delhi, India
来源：
INTERNATIONAL JOURNAL OF ADVANCED COMPUTER SCIENCE AND APPLICATIONS | 2019年 / 10卷 / 01期
关键词：
Drain Induced Barrier Lowering (DIBL); Gate Induced Drain Leakage (GIDL); Subthreshold Swing (SS); Silicon On-Insulator (SOI);
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
An improved trapezoidal pile gate bulk FinFET device is implemented with an extension in the gate for enhancing the performance. The novelty in the design is trapezoidal cross-section FinFET with stacked metal gate along with extension on both sides. Such improved device structure with additional process cost exhibits significant enhancement in the performance metrics specially in terms of leakage current behavior. The simulation study proves the suitability of the device for low power applications with improved on/off current ratio, subthreshold swing (SS), drain induced barrier lowering (DIBL), Gate Induced Drain Leakage (GIDL) uniform distribution of electron charge density along the channel and effects of Augur recombination within the channel.
引用
收藏
页码：189 / 194
页数：6
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