RF CMOS linearity analysis using harmonic balance device simulation

被引：0
|
作者：
Kopalle, D [1 ]
Niu, GF
Taylor, SS
机构：
[1] Auburn Univ, Dept Elect & Comp Engn, 200 Broun Hall, Auburn, AL 36849 USA
[2] Intel Corp, Commun Circuit Lab, Hillsboro, OR 97124 USA
来源：
2006 TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS, DIGEST OF PAPERS | 2006年
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D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Intermodulation linearity of CMOS transistors obtained from device level Harmonic Balance simulation is compared to that obtained using I-V data and good agreement between the two approaches is observed. Linearity is simulated as a function of channel length and oxide thickness. The impact of poly-gate depletion effect on linearity is also analyzed.
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页码：69 / +
页数：2
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