共 50 条
- [23] Pipelined fast 2-D DCT architecture for JPEG image compression 14TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS, 2001, : 226 - 231
- [24] CORDIC Architecture Based 2-D DCT and IDCT for Image Compression 2015 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP), 2015, : 1473 - 1477
- [26] Flipping Based High Performance Pipelined VLSI Architecture for 2-D Discrete Wavelet Transform PROCEEDINGS OF THE 2015 INTERNATIONAL CONFERENCE ON APPLIED AND THEORETICAL COMPUTING AND COMMUNICATION TECHNOLOGY (ICATCCT), 2015, : 832 - 836
- [28] A high speed array architecture for 2-D wavelet transform PROCEEDINGS OF THE 39TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, 1996, : 1239 - 1242
- [29] High-Performance TSV Architecture for 3-D ICs IEEE ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2010), 2010, : 467 - 468