Effect of technology scaling on RF performance of the transistors fabricated by standard CMOS technology

被引：0

作者：

Kim, Han-Su ^{[1
]}

Chung, Chulho ^{[1
]}

Jeong, Joohyun ^{[1
]}

Jung, Seung-Jae ^{[1
]}

Lim, Jinsung ^{[1
]}

Joe, JinHyoun ^{[1
]}

Park, Jaehoon ^{[1
]}

Lee, HyunWoo ^{[1
]}

Jo, Gwangdoo ^{[1
]}

Park, Kangwook ^{[1
]}

Kim, Jedon ^{[1
]}

Oh, Hansu ^{[1
]}

Yoon, Jong Shik ^{[1
]}

机构：

[1] Samsung Elect, Syst LSI Div, Yongin 449711, Gyeonggi Do, South Korea

来源：

2008 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM, VOLS 1 AND 2 | 2008年

关键词：

RF FET; cut-off frequency; gain; noise; drain conductance; threshold voltage;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Cut-off frequency (f(T)) of 300 GHz and 230 GHz for NMOS and PMOS is demonstrated for transistors with a gate length of 35 nm fabricated by 45 nm standard CMOS technology. Current gain (H-21) and noise (flicker and thermal) is improved with scaling down technology. Power gain (G(n)) increase is slow down and even saturated at 45 nm as technology advances. Such saturation in power gain is attributed to rapid increase in g(ds) (drain conductance). Additional efforts are required to reduce g(ds) for continuous improvement in power gain with the scaling. V-th optimization can be one of options to achieve better g(ds).

引用

页码：499 / 502

页数：4

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