Impact of technology scaling on metastability performance of CMOS synchronizing latches

In this paper, we use circuit simulations to characterize the effects of technology scaling on the metastability parameters of CMOS latches used as synchronizers. We perform this characterization by obtaining a synchronization error probability curve from a histogram of the latch delay. The main metastability parameters of CMOS latches are tau(m) and T-w. tau(m) is the exponential time constant of the rate of decay of metastability and T-w is effective size of metastability window at a normal propagation delay. Both parameters can be extracted from a histogram of the latch delay. This paper also explains a way to calibrate simulator for enough accuracy. Our simulations indicate that tau(m) scales better than the technology scale factor. T-w also scales down but its factor cannot be well estimated as that of tau(m). This is because T-w is a complex function of signal and clock edge rate and logic threshold level.