A study on memory characteristics of hybrid-based charge trap-type organic non-volatile memory device according to gate stack thickness

Continuous research on charge trap-type organic non-volatile memory (CT-ONVM) devices aims to achieve highly reliable large memory window characteristics, comparable to inorganic-based poly-silicon/oxide/nitride/ oxide/silicon (SONOS) devices. This study introduces hybrid-based ultra-thin films via the initiated chemical vapor deposition (iCVD) process as the gate-stack of highly reliable CT-ONVM devices. One method of achieving a wide memory window is by increasing the gate-stack thickness of hybrid-based gate stacks of CT-ONVM de-vices. However, thick gate-stacks (>50 nm) do not dramatically change the memory window and deteriorate the subthreshold swing (S.S.) compared to thin gate-stacks (<30 nm). Electrons passing through the thickened tunneling dielectric layer (TDL) generate a large number of interface traps, which degrade the S.S. and hinder the charge injection into the charge trapping layer (CTL). This contributes to the non-change of the memory window to increase along with the leakage through the blocking dielectric (BDL) to the gate electrode. Based on electrical characterization, our group proposes directions and follow-up plans to effectively improve the memory window and reliability of CT-ONVM devices.